The integration density, that is to say the number and density of the components used in integrated circuits, is increasing to an ever greater extent in semiconductor technology. Furthermore, leakage currents are becoming ever greater with the new semiconductor technologies. In order to limit the power consumption and the heat developed by integrated circuits, concepts must therefore be found to limit the power consumption of integrated circuits.
For this purpose, it is known for the clock signal to be masked out or switched off in areas, blocks or register banks of the integrated circuit in which it is temporarily not used, in order to reduce or completely suppress the switching activity and the switching currents associated with it in these unused blocks. In principle, a simple AND gate (NAND gate with an inverter) would be sufficient for this purpose, by means of which a clock signal that is applied to a first input can be masked out by means of an enable signal which is applied to a second input. However, the enable signal is not synchronized to the clock signal so that, when the clock signal is enabled and masked out, the switching of the enable signal generally results in additional flanks (glitches) occurring in the clock signal at the output of the AND gate.
The use of a clock control cell (gated clock cell) as illustrated in FIG. 1 is known in order to synchronize the enabling and masking out of clock signals. The output stage 1, which comprises a NAND gate NAND and an inverter 11, is preceded by a hold element (latch) 2, which synchronizes the unsynchronized enable signal EN to the input clock signal CLK1. The output signal from the hold element 2 changes its value only when the input clock signal CLK1 assumes the logic value 0. At this time, the output signal from the output stage 1 remains at the logic level 0 when changes occur in the output signal from the hold element 2, and no additional flanks (glitches) occur in the output clock signal CLK2.
Relatively recent developments in particular are intended to have the capability to switch off the supply voltage, or to match the supply voltage to the instantaneous voltage required, corresponding to the instantaneous task of the block, that is to say in general to reduce it, in areas and/or blocks which are temporarily not used.
Any change in the supply voltage to a block results in correspondingly changed voltage levels of the logic values within this block, since the voltage levels are generally defined as a function of the supply voltage. Normally, the voltage level of the logic one is identical to the supply voltage, and the voltage level of the logic zero is identical to ground.
The supply voltages for different blocks in this case are intended to be varied or switched off independently of one another. In consequence, by way of example in blocks which are connected to one another, identical logic signals are represented by different voltage levels. Thus, in the general case, the voltage levels of the logic signal values for one block represent undefined signal values for the respective other block. Furthermore, voltages which represent the logic signal value one fall only slowly after a block has been switched off, and during this time period thus form undefined logic signal values for an adjacent block. This can lead to very high parallel or short-circuit currents in the adjacent block, associated with a large power consumption and a large amount of heat. Particularly in logic CMOS circuits, the parallel current disappears only when the voltage levels of the input signals are outside a specific voltage range, which is located between the voltage levels of the logic signal values.